About Course

MicrophoneCourse is introductory level and is on VHDL (Very High Speed Integrated Circuit Hardware Description Language) and FPGA (Field Programmable Gate Arrays). It is simply the contemporary way of designing and testing digital (logic) circuits. VHDL is not a programming language. We start with simple digital circuits like driving a LED, designing a binary counter, eventually ending up with SPI communication and similar basic digital circuits. Here and here are the course and lab description documents respectively.

Slides & Handouts

MicrophoneCourse slides are provided here in pdf format. Reading the slides before the class will help a lot understanding the subject. Course may not follow the order of slides listed here.

1. Introduction and Combinatorial (slides)

2. Clocked Circuits (slides)

3. More VHDL (slides)

4. Functions and Like (slides)

Download Spartan 3E Starter Kit User Guide


Intro. to VHLD Course Labs are held in FPGA Lab. Lab documents can be downloaded from the links below. Spartan3E-kit user guide is here.

1. Starting an ISE Project (experiment)

2. 3 to 8 Decoder. (experiment, report)

3a. Up Counter. (experiment, report)

3b. Up-Down Counter ISIM simulator. (experiment, report)

3c. Key Debouncing. (homework, experiment, report)

4. Two Instances of a Counter. (experiment, report)

5. Knight Rider with Buttons (experiment, report)

6. Rotary Encoder (experiment, report)

7. Rotary Encoder N bit (experiment, report)

8. A State Machine (experiment, report)

8a. A Simple Vending Machine (experiment, report)

9. Another State Machine (experiment, report)

10. Block Memories (experiment, report)

10a. Block Memories Inference (experiment, report)

11. SPI Communication (experiment, report)

Keep in Touch

MicrophoneUnless otherwise is announced, lab reports should be mailed to


in two workdays. There may be exceptions for some experiment reports, in that case, please e-mail your reports no later than following Monday. Course instructor can be reached via eseke@ogu.edu.tr

News & Announcements

Review the slides before class. It will help a lot.

(19.11.2019) Project assignments are here.

(09.11.2019) Midterm solutions are here.

(30.10.2019) Term Projects.

(17.10.2019) Windows10 ISE file-open problem solution is here.

(02.01.2019) Final exam answers are here.

(23.12.2018) Project groups will present and demonstrate their projects this week according to the schedule.

(11.12.2018) Project assignments are here.

(13.11.2018) Midterm exam solutions vhdva_18g.pdf.

(09.11.2018) VGA project we did in the class is here.

(31.10.2018) Term Projects announcement is here.

.Students are encouraged to be a member of "ESOGU VHDL Course" Facebook group. Posting files and comments are easier in a closed group.

You may review last year's projects here.

Reading List:
1. E. Seke, VHDL Örnekleriyle Sayısal Haberleşmeye Giriş, Seçkin Yayıncılık


2. V.A. Pedroni, Circuit Design with VHDL, MIT Press.




VHDL past exams with solutions can be downloaded here. Ask related questions via eseke@ogu.edu.tr

2016g : vhd16g_va

2015g : vhd15g_va, vhd15g_fa, vhd15g_ma

2015b : vhd15b_va, vhd15b_fa

2013 : vhd13_fa, vhd13_ma, vhd13_qz2a, vhd13_1a, vhd13_2a

2012 : vhd12g_1a, vhd12g_fa, vhd12_fa

2011 : vhd11_fa, vhd11g_1a, vhd11g_2a, vhd11g_fa, vhd11_1a, vhd11_2a

2010 : vhd10_2q, vhd10g_1a, vhd10g_2a, vhd10g_fa, vhd10_1a, vhd10_2a

2009 : vhd09_fa, vhd09_1a, vhd09_2a